The present invention relates to structure and erasure methods for a sectored flash EPROM.
Floating-gate nonvolatile memories were one of the earlier semiconductor memory technologies. In such memories, a MOS transistor channel is addressed by a control gate, and is also coupled to a floating gate (which is usually interposed between the control gate and the channel). The presence of charge on the floating gate will shift the effective threshold voltage of the transistor (as seen from the control gate). Thus, the presence or absence of charge on the floating gate is detected simply by applying the appropriate read potential to the control gate, and then measuring the current passed by the transistor.
Each floating gate is totally surrounded by insulator material, so that charge on the floating gate will remain trapped for a long time. This provides the desirable nonvolatility of the memories, but means that special measures must be taken for injection and removal of trapped charge from the floating gate. Injection of electrons onto the floating gate can be accomplished by making them "hot" (i.e. passing them through a high electric field, to give them a temporary excess of energy which will permit them to travel through a dielectric), or by applying a high field to a thin dielectric, so that electrons runnel through the thin dielectric. However, removal of trapped charge is more difficult.
In the simplest type of floating-gate memory cell (an "EPROM" cell), removal of the trapped charge is not possible at all, or is possible only by flooding the chip with ultraviolet light. Obviously, this is a significant limitation on the utility of such memories. A large amount of work has therefore been invested in the development of cells which are electrically erasable ("EEPROM" or "E.sup.2 PROM" cells). Various architectures for such cells have long been known or proposed, but all have tended to suffer from disadvantages such as large cell area, special non-standard fabrication process requirements, very slow erasure, and/or very low yield. Thus, EEPROM memories have never enjoyed wide use.
Flash EPROMs (sometimes referred to simply as "flash" memories) are a relatively new memory technology. This technology retains many of the advantages of conventional EEPROMs while avoiding many of their associated problems. A flash EPROM is a memory that can be programmed, like an EPROM, by the injection of hot carriers, and is electrically erasable in bulk. Instead of the cell-by-cell erasure provided by EEPROM architectures (with the attendant problems), flash EEPROMs will erase all of the cells (or, alternatively, a large block of cells) in a single erase operation. (Physically, a flash EPROM memory cell is constituted by a floating gate transistor, the gate oxide of which has a thickness that is small and uniform (e.g. 100 .ANG.) throughout the length of the conduction channel. A large amount of work has been invested in developing flash memory cell architectures. See, e.g., Cernea et al., "A 1 Mb flash EEPROM," 1989 ISSCC DIGEST pp. 138-9, 316; Kynett et al., "A 90-ns one-million erase/program cycle 1-Mbit flash memory," 24 IEEE JOURNAL OF SOLID-STATE CIRCUITS pp. 1259-64 (October 1989); Tam et al., "A high density CMOS 1-T electrically erasable non-volatile (flash) memory technology," 1988 VLSI SYMPOSIUM DIGEST pp. 31-2; Kume et al., "A flash-erase EEPROM cell with an asymmetric source and drain structure," 1987 IEDM DIGEST pp. 560-3; Samachisa et al., "A 128K flash EEPROM using double-polysilicon technology," SC-22 IEEE JOURNAL OF SOLID-STATE CIRCUITS pp.676-83 (October 1987); Masuoka et at., "A 256-kbit flash E.sup.2 PROM using triple-polysilicon technology," SC-22 IEEE JOURNAL OF SOLID-STATE CIRCUITS 548-52 (August 1987); Masuoka et al., "A new flash E.sup.2 PROM cell using triple polysilicon technology," 1984 IEDM DIGEST pp. 464-7; all of which are hereby incorporated by reference.)
To enable users to partition their memory map, geared to a particular application, according to the nature of the information elements to be memorized and, especially, according to the frequency with which these information elements are refreshed, it has been proposed to segment the memory map of a flash EPROM into several sectors enabling the erasure of one or more or all of the sectors of the memory at one and the same time. (See, e.g., Kume et al., "A 3.42 .mu.m .sup.2 flash memory cell technology conformable to a sector erase," 1991 VLSI SYMPOSIUM DIGEST pp.77-8; McConnell et al., "An experimental 4 Mb flash EEPROM with sector erase," 26 IEEE JOURNAL OF SOLID-STATE CIRCUITS pp. 484-91 (April 1991); both of which are hereby incorporated by reference. The sectors do not necessarily have the same size. In typical applications, one 0.2 Mbit sector and another 0.8 Mbit sector are proposed for a 1 Mbit flash EPROM.
The flash EPROM memory map is erased in a known way by the application of an erasure voltage of the order of nine volts to the source of the memory cells and by connecting their gates to the ground, the drains being unconnected. The source/substrate junction of the cells is then reverse biased. The strong electrical field through the gate oxide triggers the conduction by tunnel effect at the source. The choice of the nine-volt erasing voltage corresponds to the point of optimum operation for the source of the cells to obtain the erasure by tunnel effect without any risk of prompting leakage currents in the source/substrate junction and without the risk of making this junction go into avalanche breakdown.
The segmentation of the memory map for an erasure by sectors is then based on the fact that the cells of a sector have their sources in common. FIG. 1 shows this kind of a memory map (P) of a flash EPROM divided into two sectors.
The memory map (P), in this example, comprises 256 bit lines (BL0 to BL255) and 512 word lines (WL0 to WL511).
At each intersection of a bit line and a word line, a memory cell c has its drain d connected to the bit line and its control gate g connected to a word line.
The first sector 1 covers the first 16 bit lines BL0 to BL15 and the 512 word lines WL0 to WL511. All the cells of this first sector 1 have their source connected to a first electrical node S1.
The second sector 2 covers the last 240 bit lines BL16 to BL255 and the 512 word lines WL0 to WL511. All the cells of this second sector 2 have their source connected to a second electrical node S2.
In this example, the memory map has been segmented according to the bit lines. It could be possible to segment them according to the word lines, or to combine the two types of segmentation.
A sector is defined simply as a set of memory cells having their sources connected together to one and the same electrical node.
The operation of selective erasure consists then in applying the erasing voltage to the node of the sector to be erased. This erasing voltage is applied to the node of a sector through a resistor for limiting the erasure current as shown in FIG. 1:R1 for the sector 1, R2 for the sector 2. The value of the limiting resistance for a given sector is determined on the basis of the number of cells of this sector and the expected characteristic erasure current left of a memory cell (known for a given technological method of manufacture) in such a way that the voltage applied to the common source of the sector, for example S1 for the sector 1, through this limiting resistor is about 9 volts. The point of operation of the source of the cells is then the optimum for the erasure and for the source/substrate junction.
The formula used to determine the limitation resistance is therefore the following: EQU Ve-R.multidot.n.multidot.Ieff=9 Volts,
where n is the number of cells of the sector, R the limitation resistance of the sector and left the expected erasure current for a cell.
In theory, therefore, there is the same source voltage in erasure for each of the sectors. However, in practice, the source voltage may vary from one sector to another. Indeed, the current of erasure of the sector may be greater than expected, because of the leakage currents in the cells for example. The source voltage will then be lower than expected, since the drop in voltage in the resistor will be greater.
In practice, the source voltage of one sector in erasure may be found to be (e.g.) 9.2 volts while that of another sector is 8.3 volts, because of these leakage currents.
The electrical field applied to the gate oxide will then be higher for the cells of the first sector which will therefore get erased more quickly than the second sector.
Now, if it is desired to erase both sectors at the same time, the erasure voltage Ve will be applied to both sectors for a determined duration, and then the cells will be read to check whether they are erased or not. If they are not erased, the erasing voltage will be applied and so on and so forth. If the first sector gets erased more swiftly than the second one, then so long as the second one has not been erased, the erasing voltage will continue to be applied to the two sectors. The cells of the first sector will then get depleted and the first sector will deteriorate.
This problem of the disequilibrium in the erasure speeds is a major drawback in practice because it leads to the deterioration of the flash EPROM memories divided into sectors without its being possible to control this deterioration. (See generally, e.g., Haddad et al., "Degradations due to hole trapping in flash memory cells," 10 IEEE ELECTRON DEVICE LETTERS pp. 117-19 (March 1989); Haddad et al., "An investigation of erase-mode dependent hole trapping in flash EEPROM memory cell," 11 IEEE ELECTRON DEVICE LETTERS pp. 514-16 (November 1990); both of which are hereby incorporated by reference.
In practice, this disequilibrium prevents the use of the parallel erasure of the sectors and, to erase several or all the sectors of the memory map, it is then necessary to erase them one after the other, and this is a very lengthy operation.
In the invention, the problem of disequilibrium between the speeds of erasure is resolved to enable the erasure, either of all the sectors or of several sectors in parallel in a reliable manner, without any deterioration of the memory. The invention also enables the sectors to be erased individually.
In the invention, when several sectors have to be erased in parallel, one and the same resistive path is imposed on them. The real voltage applied to the sources of the cells of these sectors will therefore be the same for all of them. If a sector has an erasure current that is smaller or greater than the one expected, the speed of erasure will be higher or lower, but it will be the same for all the sectors since the erasing voltage is applied to the sectors through a same value of resistance.
Thus, the invention proposes a device for the erasure of sectors of a memory map of a flash EPROM, the erasure of sectors being done by means of an erasing voltage applied to the source of these sectors, said device comprising resistive elements by which the erasing voltage is applied, wherein said device comprises routing means to assign a predetermined resistive element to several sectors when these sectors are selected simultaneously to be erased.
Advantageously, the routing means enable the assigning of a resistive element proper to each sector when the sectors are selected individually to be erased.
An object of the invention is also a memory comprising an erasure device such as this and the corresponding erasing method.
The disclosed innovations permit greater flexibility in designing flash memories with multiple independently erasable sectors. In particular, the disclosed flash EPROM architectures enable reliable construction and operation of memories with a relatively large number of sectors. This in turn gives greater flexibility in tailoring such memories to the requirements of users. For example, where a flash memory is used to store information which is critical to a system's reliability (as in a personal computer's BIOS), fine-grained sectoring helps to simplify the problem of protecting the system against loss of critical data due to power interruption while updating the flash memory.